The present invention relates to an organic semiconductor device, more particularly to an organic field effect transistor memory cell having an organic semiconductor material forming the field effect transistor and a ferroelectric thin film polymer as gate dielectric, and methods of fabricating such a device.
Semiconductor memories are configured as either read-only memories (ROM) such as EPROM (Electrically Programmable ROM), EEPROM (Electrically Erasable ROM), flash ROM or as volatile, random access memories (RAM) such as SRAM (Static RAM) and DRAM (Dynamic RAM). The processing required to produce these memory types are complicated and the necessary facilities are expensive due to the high temperature processing required. Ferroelectric ceramic random access memories and field effect transistor memories can be configured to be both read-write and nonvolatile, but again the processing conditions require processing at temperatures in excess of about 600xc2x0 C. Furthermore, these silicon-based or ferroelectric ceramic-based memories are expensive as the inorganic raw materials used are expensive when compared to many organic materials in addition to the high costs involved in the processing.
Ferroelectric materials possess the unique properties of a spontaneous polarization which can be re-oriented with an applied field, and that the polarization state can be retained even after the removal of electric field. Hence ferroelectric materials can contain two data states (xe2x80x9c+xe2x80x9d and xe2x80x9cxe2x88x92xe2x80x9d polarization states) which are very stable over a variety of environmental conditions. These properties allow ferroelectric materials to be one of the best materials for production of digital computer memories. Research activities on ferroelectric-based computer memories commenced in the 1950s, just following the appearance of computers. However, because these early researches focused on using bulk ferroelectric materials which required very high applied voltages to be used to re-orient the polarization, the research activities were discontinued and no commercial products developed.
In the 1980s, with the advances of ferroelectric thin film deposition technology and integration of ferroelectric thin films with silicon microelectronics, practical ferroelectric memories were developed and commercial products were introduced in the market. These advances allowed for the manufacture of ferroelectric thin film based memories which use a standard 5V or 3V voltage to re-orient the polarization or that is, to read and write data. These ferroelectric random access memories (FRAM) combine the advantages of read-on memories (ROM) and volatile random access memories. FRAM have the same advantages of DRAM and SRAM in that they are easy to write, but are superior to DRAM and SRAM due to their nonvolatility. That is, FRAM store the data even in the absence of power. FRAM also have the same advantages of EPROM, EEPROM and Flash ROM in that they are easy to read, but are superior to EPROM and EEPROM as the write speed of FRAM is much faster than that of EPROM, EEPROM and Flash ROM as well as having a higher number of allowed write cycles. However, FRAM does have one drawback. This major drawback is the destructive readout. In order to determine if the polarization of the ferroelectric thin film cell is positive (e.g., representing a xe2x80x9c0xe2x80x9d) or negative (e.g., representing a xe2x80x9c1xe2x80x9d), a positive (or a negative) pulse is applied to the cell. The induced charge will be significantly different between positively and negatively polarized ferroelectric cells. However, if the original state of the ferroelectric cell was a negative polarization state, it will change to positive polarization state after reading via a positive pulse being applied to the cell. Likewise, if the original state of the ferroelectric cell was a positive polarization state, it will change to negative polarization state after reading via a negative pulse being applied to the cell. This destructive readout requires that each read access be accompanied by a pre-charge operation to restore the memory state.
In order to solve the destructive readout problem, ferroelectric thin film-based field effect transistors (FETs) have been proposed as the next-generation ferroelectric memories. The ferroelectric FETs use a ferroelectric thin film as a gate dielectric. The ferroelectric thin film is deposited on a silicon substrate, either with or without a thin dielectric layer such as silicon dioxide (SiO2) or silicon nitride (Si3N4) between the silicon substrate and the ferroelectric thin film. When a gate voltage is applied, the polarization of the ferroelectric thin film can be either positive or negative and the polarization state can be retained after the removal of gate voltage. This positive or negative polarization can affect the source-drain current or the source-drain resistance. As the source-drain current or resistance can be controlled by the polarization state of the ferroelectric thin film, a single ferroelectric FET can be used as a memory cell. It can be seen that the ferroelectric FET memory cells have all the advantages of FRAM, such as nonvolatility, easy to read and write, lower power consumption, plus the additional advantage of a nondestructive readout. Furthermore, FRAMs utilizing ferroelectric thin films have a larger remnant polarization (usually larger than 10 xcexcC/cm2), while a remnant polarization of at the order of one-tenth xcexcC/cm2 can effectively change the source-drain current in ferroelectric FET memories.
It should be noted that all current ferroelectric FET memory cells use ferroelectric ceramic thin films such as lead zirconate titanate (PZT) or strontium bismuth tantalate (SrBi2Ta2O9 or SBT) with Si-based semiconductors. Therefore, both to deposit the ferroelectric film and to make the FET requires high temperature processes with temperatures in excess of about 600xc2x0 C. More recently, a research group in France has demonstrated (G. Velu, C. Legrand, O. Tharaud, A. Chapoton, D. Remiens, and G. Horowitz, Appl. Phys. Lett, 79, 659, 2001) the memory effect of a ferroelectric FET using PZT thin film as gate dielectric and xcex16T (sexithiophene) organic thin film transistor. The deposition of xcex16T organic thin film can be done at 100xc2x0 C., but the preparation of PZT film needs a post annealing treatment at 625xc2x0 C.
In contrast to ferroelectric ceramic thin films, ferroelectric polymer thin films, such as in the family of poly(vinyidiene-trifluoroethylene) (P(VDF-TrFE)) copolymers can be easily deposited on silicon or other substrates using solution spin coating, casting, evaporation or Langmuir-Blodgett (LB) growth method, with the growth temperature lower than 200xc2x0 C. The remnant polarization of these polymer thin films can be higher than 40 mC/m2, or 4 xcexcC/cm2, which is large enough to change the source-drain current and suitable for use in a ferroelectric memory device. Thus organic, nonvolatile, nondestructive readout ferroelectric memory cells can be developed by combining ferroelectric polymer thin film technology and organic thin film transistor technology.
There is provided a FET memory cell that comprises a substrate which could be made from a wide variety of materials such as silicon, metal, glass, or plastic, a polymer ferroelectric thin film gate dielectric such as P(VDF-TrFE) copolymer thin film, an organic thin film semiconductor such as a pentacene film, and gate, source, and drain electrodes which could be constructed using a variety of conducting materials such as a thin metal film, conducting oxide, or conducting polymer. The memory cell may also contain a dielectric polymer layer between the ferroelectric polymer thin film and the organic semiconductor thin film and a floating gate electrode.
There are many candidate ferroelectric polymer materials that can be used in the above memory structures, including but not limited to poly(vinylidene fluoride) (PVDF), poly(vinyidiene-trifluoroethylene) (P(VDF-TrFE)) copolymers, odd-numbered nylons, cyanopolymers, polyureas and polythioureas. Thin films of these polymers can be produced by solution spin coating or solution casting, Langmuir-Blodgett (LB) monolayer growth method, and vapor deposition polymerization process. Typically these deposition processes can be done below 200xc2x0 C. A typical process to produce P(VDF-TrFE) copolymer thin films by solution spin coating method has been described in Q. M. Zhang, H. Xu, F. Fang, Z. Y. Cheng, F. Xia, and H. You, J. Appl. Phys., 89, 2613, 2001. The steps in this typical process include first dissolving P(VDF-TrFE) copolymers in the composition range from 50/50 to 80/20 mol % in dimethylformide (DMF), with a resulting concentration ranging from 4 wet % to 12 wet %. Then the solution is used in a spin coating process to provide a film. It is well known in the art that films with various thicknesses can be obtained by controlling the spin conditions and/or using a process which uses multiple coating procedure. Finally the films are annealed at 140xc2x0 C. under vacuum to remove the residual solvent and to improve the crystallization. This process can obtain films with a thickness between 120 nm to more than 1 xcexcm and remnant polarization of more than 40 mC/m2. An alternative process uses the Langmuir-Blodgett deposition method to obtain P(VDF-TrFE) 70/30 copolymer films, with thickness of 5000 xc3x85 to 5 xc3x85.
There are organic semiconductor thin film materials that can be used in the memory cells in this invention, include but are not restricted to poly(phenylenes), thiophene oligomers, pentacene, polythiophene, and perfluoro copper phthalocyanine. While a wide variety of organic semiconductor thin films materials are suitable, it is believed that those materials with high mobility or high current modulation Ion/Ioff are preferred as the source-drain current of such materials is more sensitive to an applied gate voltage. It is believed that the higher sensitivity to an applied gate voltage will result in improved read/write characteristics. Examples of these materials include pentacene, and xcex1-xcfx89-dihexylhexathiophene (DH6T). The thickness of the organic semiconductor thin films can be in the range of approximately 5 nm to approximately 5 xcexcm, with a preferred range of approximately 50 nm to approximately 200 nm and more preferrably a thickness of approximately 100 nm.
These organic thin film semiconductors can be made by well known processes such as vacuum evaporation, electrochemical polymerization, solution spin coating, screen printing, ink jet printing, and Langmuir-Blodgett growth. For example, pentacene thin films can be produced by using vapor deposition with the substrate temperatures from room temperature to 120xc2x0 C. as described in C. D. Dimitrakopoulos, B. K. Furman, T. Graham, S. Hegde, and S. Purushothaman, Synth. Met., 92, 47, 1998, or by solution spin coating method using dichloromethane as solvent and annealing temperatures of 140 to 180xc2x0 C. as described in A. R. Brown, A. Pomp, D. M. de Leeuw, D. B. M. Klaassen, E. E. Havinga, P. Herwig, and K. Mullen, J. Appl. Phys., 79, 2136, 1996.
Silicon wafers and silicon oxide grown on silicon wafers have been widely used as substrates and gate dielectric to make organic thin film FETs. Organic thin film FETs have also been built on glass substrates and plastic polyster substrates, and using organic polyimide, polyvinyl alcohol (PVA), polyvinyl chloride (PVC), and polymethylmethacrylate (PMMA) as gate dielectric as described in X. Peng, G. Horowitz, D. Fichiou, and F. Garnier, Appl. Phys. Lett., 57, 2013, 1990; Z. Bao, Y. Fang, A. Dodabalapur, V. R. Raju, and A. J. Lovinger, Chem. Mater., 9, 1299, 1997. Evaporated or sputtered metal electrodes such as gold, platinum, or aluminum, evaporated or printed conducting oxides such as Indium-Tin oxide (ITO) and conducting polymers such as polyaniline have been used as electrodes for organic thin film FETs as described in Z. Bao, Y. Fang, A. Dodabalapur, V. R. Raju, and A. J. Lovinger, Chem. Mater., 9, 1299, 1997; G. Gustagsson, Y. Cao, G. M. Treacy, F. Klavetter, N. Colaneri, and A. J. Heeger, Nature, 357, 277, 1992. It has also been reported that conducting polymer electrodes can improve the performance of ferroelectric P(VDF-TrFE) thin films by Z. Y. Cheng, H. S. Xu, J. Su, Q. M. Zhang, P. C. Wang, and A. G. MacDiarmid, Proc. SPIE, 3669, 140, 1999.
A typical sequence used in the fabrication of the proposed memory cells includes the following general steps which will be discussed in more detail below:
1). Selection of substrates and preparation of the gate electrode. The substrate could be any of, but not limited to, silicon, metal, glass and plastic or any other material that can withstand the temperatures of approximately 200xc2x0 C. used during some of the subsequent processing steps. The substrate may be either rigid or flexible, as the organic thin film semiconductors and ferroelectric polymer thin films can be flexed.
The gate electrode could be any patterned conductive material such as a metal thin film, for instance gold, platinum, aluminum, or titanium, a conducting oxide such as ITO, or a conducting polymer such as polyaniline, and polypyrrol on the surface of the substrate.
If a conducting material is used for the substrate, such as doped silicon substrates or metal substrates, then the substrate should include a thin insulating layer on the upper surface in order to isolate the gate electrodes from the substrate. For instance a silicon wafer could have a thin layer of oxidization or nitride on the upper surface as an insulator. For a metal substrate, a thin inorganic insulating layer, such silicon oxide or silicon nitride, or a thin organic insulating layer, such as polyimide, may be used. Such thin organic insulating layers may be deposited on the surface by using well known sputtering, chemical vapor deposition, or solution deposition method. The insulating layers described above are for descriptive use only, and other insulating layers may also be used.
The gate electrode could be deposited by the well known methods of evaporation, sputtering, screen or jet printing, solution dip or spin coating depending on which process is most suitable for the electrode, material and substrate being used.
2). Deposition of ferroelectric polymer thin films to form the gate dielectrics. While ferroelectric polymer materials in the family of P(VDF-TrFE) copolymers are suitable, other ferroelectric polymer materials such as PVDF, odd-numbered nylons, cyanopolymers, polyureas and polythioureas could also be used. These polymer thin films could be deposited by evaporation, solution casting or spin coating, Langmuir-Blodgett growth method, screen printing or jet printing.
3). Deposition of organic semiconductor thin films on top of the ferroelectric polymer thin films. The organic semiconductor materials can be, but not limited to, poly(phenylenes), thiophene oligomers, pentacene, polythiophene, and perfluoro copper phthalocyanine. These organic semiconductor thin films used can be deposited by vapor deposition, solution casting or spin coating, screen printing or jet printing, Langmuir-Blodgett growth method or self assembly of layers from solution or other methods.
4). Fabrication of source and drain electrodes on the top surface of the organic semiconductor thin films. The materials and processes are similar to the deposition of gate electrodes discussed hereinabove.
While the basic steps have been described above there are several optional steps that may also be used. These optional steps are described below.
One optional step is to deposit a thin polymer dielectric layer between the ferroelectric polymer thin film and organic semiconductor thin film. This thin polymer dielectric layer could be polyimide, PVA, PVC, PMMA, and PVDF and P(VDF-TrFE) in paraelectric state. This thin polymer dielectric layer can be deposited by, but not restricted to evaporation, solution casting or spin coating, and screen printing or jet printing.
Another optional step is to deposit a thin conducting layer between the ferroelectric polymer thin film and the thin polymer dielectric layer. The choice of materials and the deposition there of is similar to the deposition of gate electrodes discussed hereinabove.
Another optional step is to apply a passivation coating as the last step to protect the memory cell by chemical or physical vapor deposition, sputtering, solution spin or dip coating and curing.
The sequences of the steps to deposit gate electrode, ferroelectric polymer thin film, organic semiconductor thin film, and source and drain electrodes could be altered or revised to make various alternative structures of the memory cells and to allow process compatibility and ease of fabrication. The variation of electrode materials, ferroelectric polymer thin film materials, organic semiconductor thin film materials, polymer thin dielectric materials, and the variation of the sequences of the steps to deposit these materials are included within the spirit and scope of this invention.